📖 Biography

I’m currently a master student for Integrated Circuit Science and Technology in the School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, China, under the supervision of Prof. Hailong Jiao at VLSI-Lab. I received the B.S. degree of Microelectronics Science and Technology in Hongyi Honor College, Wuhan University, China, in June 2025, graduating with the highest GPA (3.97/4.00, Rank 1/25). My undergraduate advisor was Prof. Sheng Chang.

💡 Research Tracks

My current research interests focus on Efficient AI Chip and System.

• Accelerators for Energy Efficient Edge AI
  • I am currently dedicated to develop edge accelerators for the foundation models of physical AI, with specific scenarios like autonomous driving, robotics, etc. For a typical foundation model, I focus on hardware acceleration of the following aspects:
  • Feature Extraction: CNNs for classification, segmentation, and object detection (TCAD’24, TCAS-I’25, TC’25), and 3D visual perception networks based on point cloud.
  • Multi-Sensor Fusion: BEV-based approaches for fusing multi-view visual features in the autonomous driving scenario.
  • Scene Representation: Emerging 3D/4D representation forms such as gaussian splatting.
  • Cognition-to-Action Generation: The co-processing of high-level cognition and low-level action-making based on emerging model architectures.
• Computing-in-Memory for Emerging Applications
  • I am interested in the SRAM-based digital CIM design. I have made various review reports about SRAM CIM in my course projects, in which I advocate understanding the role of CIM in AI chips and systems from the perspectives of the abstraction hierarchy and memory hierarchy of computer systems.
• System Architecture and Design Automation for AI Deployment
  • I also make efforts on the system architecture and design automation for AI deployment, especially the design and mapping strategies for spatial dataflow architecture (TCAS-I’25).
• Fundamental Optimization Theories for AI Chip and System
  • I believe that the summarization of fundamental theories is the most important factor driving research progress. I am trying to make some contributions on review papers about fundamental theories.

🔥 News

• 2025.06:   One co-authored paper about fully pipelined FPGA accelerator for semantic segmentation CNN is accepted by IEEE TC. Congratulations to Jiahui!
• 2025.06:   One co-first-authored paper about fully pipelined FPGA accelerator and mapping toolchain for various CNN is accepted by IEEE TCAS-I. Congratulations to Zhan Li!
• 2024.09:   One co-first-authored paper about fully pipelined FPGA accelerator for encoder-decoder segmentation CNN is accepted by IEEE TCAD. Congratulations to Zhan Li!
• 2024.07:   Our fully pipelined streaming architecture for sparse Transformer acceleration wins National First Prize and YMTC (长江存储) Corporate Award in 2024 China Postgraduate IC Innovation Competition. Congratulations to Zhan Li, Qunkang and Zhihan!
• 2023.12:   Our fully pipelined streaming architecture for CNN acceleration wins National First Prize and Xilinx Corporate Award in FPGA Innovation Design Track of 2023 National College Students’ Embedded Chip and System Design Competition. Congratulations to Zhan Li, Zhihan and Xingyu!

📝 Publications

(*: co-first author)

TCAS-I 2025

MetaAccel: A High-Performance and Agile Accelerator Design Framework With Multi Clock Domain Optimization for Complex CNN

Zhan Li*, Yuxian Jiang*, Zhihan Zhang, Jiahui Huang, Qunkang Meng, Xingyu Shi, Hao Wang, Qijun Huang, and Sheng Chang

IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2025

TC 2025

A High-Intensity Solution of Hardware Accelerator for Sparse and Redundant Computations in Semantic Segmentation Models

Jiahui Huang*, Zhan Li*, Yuxian Jiang, Zhihan Zhang, Hao Wang, and Sheng Chang

IEEE Transactions on Computers (TC), 2025

TCAD 2024

PEDSA: High-Throughput Pipeline-Based FPGA Accelerator for Convolutional Encoder–Decoder Segmentation Networks

Yuxian Jiang*, Zhan Li*, Zhihan Zhang, Hao Wang, and Sheng Chang

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024

🏆 Honors and Awards

• 2025.06:   Full Tuition Credit Refund for Top 1% of 2025 Graduates at Wuhan University (武汉大学2025届前1%优秀毕业生返还全部学分费).
• 2025.06:   Outstanding Graduate of Wuhan University.
• 2025.06:   Outstanding Graduate of Hongyi Honor College, Wuhan University.

🤔 Research Taste

Personally, I conduct my research with certain research tastes. I also hope to have more exchanges with like-minded scholars.

• 📖Make ideas fall on hardware-level new features when designing accelerators: Currently, software-hardware co-design is the mainstream technique of AI accelerator. However, this does not mean that we only need to simply modify the algorithm and provide a straightforward hardware implementation. (1) Over-reliance on algorithm modification is essentially escaping hardware design difficulties by forcibly eliminating the problem itself. (2) Methods for improving algorithm efficiency also should not be blindly transferred to hardware (otherwise it will easily cause additional overhead), but rather we should look for hardware-efficient ways to support them. (3) The most meaningful co-design happens when the algorithm modification takes substantive hardware reconstruction and improvement as the start point.
• 🎯Focus on fundamental problems that closely related to most algorithms or scenarios: Directly selecting a new or specific algorithm and implementing a chip for it is an effective way to publish papers. However, I prefer to focus on more fundamental problems. Research should focus on accelerating fundamental models or operators, rather than implementing additional processing steps that are less common but just easy to find ideas for. This is also an important point to deal with the mismatch between the long implementation cycle of hardware and the rapid iteration of algorithm.
• ⚖️Find a balance between industry needs and academic significance: The value of a work should be demonstrated by combining real industry pain points and user needs with the research content, rather than broadly pursuing increasingly extreme so-called optimizations. At the same time, it is essential to distinguish between scientific and engineering problems. Academic research needs to be exploratory and groundbreaking, rather than being judged solely on whether it can be transformed directly into a product in the present moment, or being implemented by applying the thinking of product development.
• ✍️Emphasize the summary of fundamental theories: Theories like the roofline model, abstraction hierarchy, and memory hierarchy are the source of new ideas. Research should not be approached in a fast-food style; instead, one should strive to truly understand the essence and limitations behind mainstream or non-mainstream approaches, thereby improving the quality of one’s own ideas.

At the same time, I deeply admire and advocate Mr. Liang Shuming’s discussion of the eight levels of thinking.

• Level 1: Forming Your Own Opinion (形成主见)
• Level 2: Discovering Unexplainable Things (发现不能解释的事情)
• Level 3: Achieving Integration and Mastery (融会贯通)
• Level 4: Recognizing Your Own Limitations (知不足)
• Level 5: Mastering Complexity through Simplicity (以简御繁)
• Level 6: Applying Knowledge with Ease (运用自如)
• Level 7: Gaining a Panoramic View (一览众山小)
• Level 8: Achieving Thorough Clarity (通透)

I also have my own summary of research capabilities, which I believe is important for the long-term development of a student.

• On the Primary Purpose of Graduate Studies
  • The primary goal of pursuing a master or Ph.D. degree is not merely to publish as many papers as possible, nor to make grand contributions to human progress. Rather, it is to cultivate the capability to identify, analyze, and solve problems. Papers and tangible outcomes are the “fish” (the product), not the “fishing” (the thinking, method, and spirit).
• The Three Pillars of Research Competence
  • Knowledge and Skills:
    • Have you solidified your foundational knowledge? Can you properly and effectively write code? Are you proficient with software tools and experimental instruments? At the level of a practitioner, you must learn to keep your hands dirty — that is, to be willing to tackle tasks step by step and implement them with dedication.
  • Research Thinking:
    • Domain-Specific Research Cognition:
      • Do you possess a comprehensive and clear overall understanding of a particular field or industry?
      • For your specific research area, are you familiar with the entire relevant knowledge system?
      • Do you understand the major problems to be solved, the traditional approaches, the emerging methods, and your own approach (if any), as well as possible future directions?
      • Can you work with clear motivation and logic, rather than busying yourself without clarity?
    • Universal Learning Capability:
      • Are you enable to quickly grasp the underlying logic of new subjects or domains?
      • Can you efficiently “learn on the fly” and apply new knowledge promptly, rather than remaining at the stage of exam-oriented cramming, ineffective rote memorization, or working within artificially limited scopes?
  • Information Expression
    • Internal Communication with Colleagues: As a team member, can you clearly communicate with collaborators about: what you have accomplished, what problems you have encountered, and what you need from them?
    • External Communication with Others: As a leader, can you effectively convey the value of your project or proposal to others, thereby securing resources and opportunities for your team? As an author, can you present your work persuasively to peer reviewers, enabling them to approve your manuscript for publication?

🚀 Projects

Point Cloud Transformer Accelerator [Tape-Out May 2025] – Peking University & Wuhan University – September 2024 to May 2025

This work proposed a $2 \times 3\ \mathrm{mm}^2$ TSMC 28nm accelerator for transformer-based point cloud understanding, leaded by Dr. Yanzhe Ma and Dr. Changchun Zhou.

Main Contributions:

1. Implementation of 3 basic operation units, including element-wise add/sub, tensor concatenation, and matrix transposition. The 3 units support a modified AXI interface and arbitary tensor sizes.
2. Implementation of a UART unit. This unit supports 2 modes. The monitor mode transfers on-chip signals that are pre-defined to be monitored from chip to external host. The external memory access (EMA) mode transfers module instructions from external memory to on-chip top controller through request sending and data receivement with bi-direct UART-AXI conversion.
3. Assistance in the implementation of the on-chip AXI crossbar, fast point sampling (FPS) unit, and the byte-enable-supported global buffer.
4. Verification of a embedded RISC-V core which is for write/read the on-chip config regfile through software.

Video Codec 4D Gaussian Splatting Accelerator [Tape-Out May 2026] – Peking University – August 2025 to May 2026

This work proposed a $2 \times 2\ \mathrm{mm}^2$ TSMC 28nm accelerator for i3DV/HAC-style Video Codec 4D Gaussian Splatting (VC-4DGS) to enable streaming decoding-to-rendering in mobile devices, leaded by master student Wei Luo.

Main Contributions:

1. Implementation of a multi-resolution binary hash interpolation unit. This unit supports tri-linear interpolation based on multi-resolution binary hash grid, which is used for scene feature decoding of I-frame and P-frame. The output of this unit, i.e. scene context, serves as the basic of subsequent entropy decoding and MLP. A fully pipelined memory-to-compute dataflow is implemented based on the operation intensity characteristics and dimension reorganization of the hash grid. A vertex pre-aggregated compute core reduces redundant, high bit-width computations through reformulation.
2. Implementation of a gaussian preprocess unit. This unit supports complete functions for converting 3D gaussian properties (3D covariance matrix and spatial coordinate mainly) to 2D splatted gaussian properties (2D covariance matrix and pixel scale coordinate) in a fully pipelined manner. The conversions involve linear transformations based on view-transformation matrix and projection matrix, quadratic-form-style covariance splatting based on Jacobi matrix, generation of the inverse matrix based on determinant, and other vector operations or scalar operations. The fixed point and scaled INT data formats are supported to maintain the accuracy.
3. Implementation of a frustum culling unit. This unit introduces NeRF-style ray sampling method into Gaussian Splatting for redundancy-check-free voxel-wise frustum culling.

Fully Pipelined Streaming Architecture and Mapping Toolchain for Various CNNs in FPGA – Wuhan University – July 2023 to June 2025

This work proposed a fully pipelined FPGA accelerator with an agile mapping framework for various CNNs, including image classification, object detection, and semantic segmentation, leaded by Dr. Zhan Li.

Main Contributions:

1. Implementation of our proposed on-chip fully unrolled parallel dataflow on ResNet18, SegNet-Basic, and U-Net.
2. Assistance in the implementation of a network-architecture-aware hardware resource estimation model based on our proposed dataflow. The model can directly generated hyper-parameters for hardware design based on user-defined performance requirement, network architecture, and target platform.
3. Implementation of a series of RTL code templates for agile synthesis of accelerators. The templates are fully parameterized, supporting arbitary common specifications of network layers (convolution kernel size, feature map size, etc.) and most types of operators in CNN, including vanilla/depth-wise/point-wise convolution, max/avg pooling, unpooling, deconvolution, and dilated convolution.

🛠️ Skills

• Coding Languages: Verilog/SystemVerilog, Python, C/C++, MATLAB
• Develop Tools: NCSim, Genus, Virtuoso, Vivado, Quartus, ModelSim, Verilator, Conda, Docker, Git, Visual Studio Code, Visual Studio, MobaXterm
• Productivity Tools: Microsoft Office (Word, PowerPoint, Excel), Markdown, LaTeX, WPS Office
• Drawing Tools: PowerPoint, Visio, Draw-io, Inkscape, Acrobat, Photoshop
• Agents: Kimi, DeepSeek Harness, GitHub Copilot

⭐️ Personal Hobbies

• 🏓Table Tennis: I am now a key member and vice-captain of the PKUSZ table tennis team. I was formerly the captain of the WHU Hongyi Honor College table tennis team. I play with a right-handed shake-hand grip (Butterfly Viscaria FL), using inverted rubbers on both sides of the blade (Forehand: DHS Hurricane 3, Backhand: Butterfly D09c). My primary scoring strategies are defense, rallies, and variations in rhythm.
• 🎹Piano: I have been learning piano since I was a child. I became very interested in ACG piano during high school and have practiced many Animenz’s arrangements, such as Unravel, Bios (10th Anniversary Edition), and Sincerely, etc. I also publish my piano arrangements on my bilibili account.
• 📜Calligraphy: During my childhood, I practiced calligraphy for many years under the guidance of Mr. Lin Zhenhong. I mainly studied classic styles such as Mr. Yan Zhenqing’s regular script and Mr. Wang Xizhi’s running script, and created many calligraphy works.
• ☯️Chinese Kungfu: I studied Chen-style Tai Chi for many years during my primary and secondary school years. I have also maintained a close interest in various kickboxing and Muay Thai competitions, such as K-1, Glory, ONE Championship, and WLF (Wu Lin Feng), etc.
• 🧐Religious Philosophy and Chinese Culture: My early years were steeped in the recitation of many traditional Chinese classics, such as the Analects, the Great Learning, the Doctrine of the Mean, and the Book of Changes. I also have an ongoing inquiry of Vedanta philosophy from India, the integral framework and evergreen philosophy of Ken Wilber, and the teachings of Krishnamurti.

🏠 Contact

• Address: Room 207, Building A, Peking University Shenzhen Graduate School, Nanshan District, Shenzhen, Guangdong, China
• Email: yxjiang25@stu.pku.edu.cn